<dec f='src/src/sys/arch/x86/include/cacheinfo.h' l='10' type='u_int'/>
<offset>32</offset>
<doc f='src/src/sys/arch/x86/include/cacheinfo.h' l='10'>/* #entries for TLB, bytes for cache */</doc>
<use f='src/src/sys/arch/x86/x86/cpu.c' l='250' u='r' c='cpu_vm_init'/>
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<use f='src/src/sys/arch/x86/x86/identcpu.c' l='237' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='242' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='248' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='253' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='258' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='263' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='278' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='295' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='314' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='319' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='324' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='329' u='w' c='cpu_probe_amd_cache'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='584' u='w' c='cpu_probe_c3'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='589' u='w' c='cpu_probe_c3'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='594' u='w' c='cpu_probe_c3'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='603' u='w' c='cpu_probe_c3'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='623' u='w' c='cpu_probe_c3'/>
<use f='src/src/sys/arch/x86/x86/identcpu.c' l='627' u='w' c='cpu_probe_c3'/>
