/** * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers * * @rdev: radeon_device pointer * @vclk: wanted VCLK * @dclk: wanted DCLK * @vco_min: minimum VCO frequency * @vco_max: maximum VCO frequency * @fb_factor: factor to multiply vco freq with * @fb_mask: limit and bitmask for feedback divider * @pd_min: post divider minimum * @pd_max: post divider maximum * @pd_even: post divider must be even above this value * @optimal_fb_div: resulting feedback divider * @optimal_vclk_div: resulting vclk post divider * @optimal_dclk_div: resulting dclk post divider * * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs). * Returns zero on success -EINVAL on error. */