<def f='src/src/sys/external/bsd/drm2/dist/drm/radeon/radeon.h' l='1460' ll='1482'/>
<size>264</size>
<mbr r='radeon_dpm_dynamic_state::vddc_dependency_on_sclk' o='0' t='struct radeon_clock_voltage_dependency_table'/>
<mbr r='radeon_dpm_dynamic_state::vddci_dependency_on_mclk' o='128' t='struct radeon_clock_voltage_dependency_table'/>
<mbr r='radeon_dpm_dynamic_state::vddc_dependency_on_mclk' o='256' t='struct radeon_clock_voltage_dependency_table'/>
<mbr r='radeon_dpm_dynamic_state::mvdd_dependency_on_mclk' o='384' t='struct radeon_clock_voltage_dependency_table'/>
<mbr r='radeon_dpm_dynamic_state::vddc_dependency_on_dispclk' o='512' t='struct radeon_clock_voltage_dependency_table'/>
<mbr r='radeon_dpm_dynamic_state::uvd_clock_voltage_dependency_table' o='640' t='struct radeon_uvd_clock_voltage_dependency_table'/>
<mbr r='radeon_dpm_dynamic_state::vce_clock_voltage_dependency_table' o='768' t='struct radeon_vce_clock_voltage_dependency_table'/>
<mbr r='radeon_dpm_dynamic_state::samu_clock_voltage_dependency_table' o='896' t='struct radeon_clock_voltage_dependency_table'/>
<mbr r='radeon_dpm_dynamic_state::acp_clock_voltage_dependency_table' o='1024' t='struct radeon_clock_voltage_dependency_table'/>
<mbr r='radeon_dpm_dynamic_state::valid_sclk_values' o='1152' t='struct radeon_clock_array'/>
<mbr r='radeon_dpm_dynamic_state::valid_mclk_values' o='1280' t='struct radeon_clock_array'/>
<mbr r='radeon_dpm_dynamic_state::max_clock_voltage_on_dc' o='1408' t='struct radeon_clock_and_voltage_limits'/>
<mbr r='radeon_dpm_dynamic_state::max_clock_voltage_on_ac' o='1504' t='struct radeon_clock_and_voltage_limits'/>
<mbr r='radeon_dpm_dynamic_state::mclk_sclk_ratio' o='1600' t='u32'/>
<mbr r='radeon_dpm_dynamic_state::sclk_mclk_delta' o='1632' t='u32'/>
<mbr r='radeon_dpm_dynamic_state::vddc_vddci_delta' o='1664' t='u16'/>
<mbr r='radeon_dpm_dynamic_state::min_vddc_for_pcie_gen2' o='1680' t='u16'/>
<mbr r='radeon_dpm_dynamic_state::cac_leakage_table' o='1728' t='struct radeon_cac_leakage_table'/>
<mbr r='radeon_dpm_dynamic_state::phase_shedding_limits_table' o='1856' t='struct radeon_phase_shedding_limits_table'/>
<mbr r='radeon_dpm_dynamic_state::ppm_table' o='1984' t='struct radeon_ppm_table *'/>
<mbr r='radeon_dpm_dynamic_state::cac_tdp_table' o='2048' t='struct radeon_cac_tdp_table *'/>
