<dec f='src/src/sys/dev/pci/pciidevar.h' l='102' type='bus_size_t'/>
<offset>2880</offset>
<doc f='src/src/sys/dev/pci/pciidevar.h' l='98'>/*
	 * Some controllers might have DMA restrictions other than
	 * the norm.
	 */</doc>
<use f='src/src/sys/dev/pci/pciide_common.c' l='151' u='w' c='pciide_common_attach'/>
<use f='src/src/sys/dev/pci/pciide_common.c' l='607' u='r' c='pciide_dma_table_setup'/>
<use f='src/src/sys/dev/pci/pciide_common.c' l='607' u='r' c='pciide_dma_table_setup'/>
<use f='src/src/sys/dev/pci/pciide_common.c' l='666' u='r' c='pciide_dma_table_setup'/>
<use f='src/src/sys/dev/pci/pciide_common.c' l='607' u='r' c='pciide_dma_table_teardown'/>
<use f='src/src/sys/dev/pci/satalink.c' l='482' u='w' c='sii3112_chip_map'/>
