<dec f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/include/subdev/bios/pll.h' l='63' type='u8'/>
<offset>120</offset>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/include/subdev/bios/pll.h' l='55'>/*
	 * for most pre nv50 cards setting a log2P of 7 (the common max_log2p
	 * value) is no different to 6 (at least for vplls) so allowing the MNP
	 * calc to use 7 causes the generated clock to be out by a factor of 2.
	 * however, max_log2p cannot be fixed-up during parsing as the
	 * unmodified max_log2p value is still needed for setting mplls, hence
	 * an additional max_usable_log2p member
	 */</doc>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/bios/nouveau_subdev_bios_pll.c' l='262' u='w' c='nvbios_pll_parse'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/bios/nouveau_subdev_bios_pll.c' l='316' u='w' c='nvbios_pll_parse'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/bios/nouveau_subdev_bios_pll.c' l='318' u='w' c='nvbios_pll_parse'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/bios/nouveau_subdev_bios_pll.c' l='343' u='w' c='nvbios_pll_parse'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/bios/nouveau_subdev_bios_pll.c' l='417' u='w' c='nvbios_pll_parse'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_pllnv04.c' l='53' u='r' c='getMNP_single'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/subdev/clock/nouveau_subdev_clock_pllnv04.c' l='154' u='r' c='getMNP_double'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/dispnv04/nouveau_dispnv04_hw.c' l='284' u='r' c='nouveau_hw_fix_bad_vpll'/>
