<dec f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nv50.h' l='130' type='struct nv50_disp_chan'/>
<offset>0</offset>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='175' u='a' c='nv50_disp_dmac_dtor'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='183' u='m' c='nv50_disp_dmac_init'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='186' u='a' c='nv50_disp_dmac_init'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='216' u='m' c='nv50_disp_dmac_fini'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='231' u='a' c='nv50_disp_dmac_fini'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='440' u='a' c='nv50_disp_mast_init'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nv50.c' l='488' u='a' c='nv50_disp_mast_fini'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='78' u='m' c='nvd0_disp_dmac_init'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='81' u='a' c='nvd0_disp_dmac_init'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='112' u='m' c='nvd0_disp_dmac_fini'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='128' u='a' c='nvd0_disp_dmac_fini'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='306' u='a' c='nvd0_disp_mast_init'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/nouveau/core/engine/disp/nouveau_engine_disp_nvd0.c' l='350' u='a' c='nvd0_disp_mast_fini'/>
