<dec f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_drv.h' l='917' type='void intel_update_watermarks(struct drm_crtc * crtc)'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='3739' u='c' c='ironlake_crtc_enable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='3884' u='c' c='haswell_crtc_enable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='3982' u='c' c='ironlake_crtc_disable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='4029' u='c' c='haswell_crtc_disable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='4417' u='c' c='valleyview_crtc_enable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='4456' u='c' c='i9xx_crtc_enable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='4532' u='c' c='i9xx_crtc_disable'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='7898' u='c' c='intel_crtc_cursor_set'/>
<def f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='2777' ll='2783' type='void intel_update_watermarks(struct drm_crtc * crtc)'/>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_pm.c' l='2745'>/**
 * intel_update_watermarks - update FIFO watermark values based on current modes
 *
 * Calculate watermark values for the various WM regs based on current mode
 * and plane configuration.
 *
 * There are several cases to deal with here:
 *   - normal (i.e. non-self-refresh)
 *   - self-refresh (SR) mode
 *   - lines are large relative to FIFO size (buffer can hold up to 2)
 *   - lines are small relative to FIFO size (buffer can hold more than 2
 *     lines), so need to account for TLB latency
 *
 *   The normal calculation is:
 *     watermark = dotclock * bytes per pixel * latency
 *   where latency is platform &amp; configuration dependent (we assume pessimal
 *   values here).
 *
 *   The SR calculation is:
 *     watermark = (trunc(latency/line time)+1) * surface width *
 *       bytes per pixel
 *   where
 *     line time = htotal / dotclock
 *     surface width = hdisplay for normal plane and 64 for cursor
 *   and latency is assumed to be high, as above.
 *
 * The final value programmed to the register should always be rounded up,
 * and include an extra 2 entries to account for clock crossings.
 *
 * We don&apos;t use the sprite, so we can ignore that.  And on Crestline we have
 * to set the non-SR watermarks to 8.
 */</doc>
