<dec f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_sdvo_regs.h' l='90' type='u8'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_sdvo.c' l='849' u='w' c='intel_sdvo_get_dtd_from_mode'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_sdvo.c' l='873' u='r' c='intel_sdvo_get_mode_from_dtd'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_sdvo.c' l='875' u='r' c='intel_sdvo_get_mode_from_dtd'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_sdvo.c' l='883' u='r' c='intel_sdvo_get_mode_from_dtd'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_sdvo.c' l='887' u='r' c='intel_sdvo_get_mode_from_dtd'/>
<offset>24</offset>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_sdvo_regs.h' l='86'>/**
		* 2 high bits of hsync offset, 2 high bits of hsync width,
		* bits 4-5 of vsync offset, and 2 high bits of vsync width.
		*/</doc>
