<dec f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_drv.h' l='396' type='_Bool'/>
<offset>13200</offset>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='5088' u='w' c='i9xx_update_pll_dividers'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='5093' u='w' c='i9xx_update_pll_dividers'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='5568' u='r' c='i9xx_set_pipeconf'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='6671' u='w' c='ironlake_crtc_mode_set'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='6673' u='w' c='ironlake_crtc_mode_set'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='7171' u='w' c='haswell_crtc_mode_set'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/intel_display.c' l='8457' u='r' c='intel_decrease_pllclock'/>
