<dec f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='579' type='2'/>
<doc f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_drv.h' l='579'>/* gen7+, L3 sits between the domain specifc
			      caches, eg sampler/render caches, and the
			      large Last-Level-Cache. LLC is coherent with
			      the CPU, but L3 is only visible to the GPU. */</doc>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='4331' c='i915_gem_get_caching_ioctl'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem_context.c' l='246' u='r' c='__create_hw_context'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem_gtt.c' l='173' c='snb_pte_encode'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem_gtt.c' l='195' c='ivb_pte_encode'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gpu_error.c' l='1278' c='i915_cache_level_str'/>
