<dec f='src/src/sys/external/bsd/drm2/dist/uapi/drm/i915_drm.h' l='812' type='__u32'/>
<offset>32</offset>
<doc f='src/src/sys/external/bsd/drm2/dist/uapi/drm/i915_drm.h' l='806'>/**
	 * Cacheing level to apply or return value
	 *
	 * bits0-15 are for generic caching control (i.e. the above defined
	 * values). bits16-31 are reserved for platform-specific variations
	 * (e.g. l3$ caching on gen7). */</doc>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='4332' u='w' c='i915_gem_get_caching_ioctl'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='4336' u='w' c='i915_gem_get_caching_ioctl'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='4340' u='w' c='i915_gem_get_caching_ioctl'/>
<use f='src/src/sys/external/bsd/drm2/dist/drm/i915/i915_gem.c' l='4359' u='r' c='i915_gem_set_caching_ioctl'/>
