<dec f='src/src/sys/dev/pci/pciide_piix_reg.h' l='49'/>
<use f='src/src/sys/dev/pci/piixide.c' l='400' u='c'/>
<use f='src/src/sys/dev/pci/piixide.c' l='414' u='c'/>
<use f='src/src/sys/dev/pci/piixide.c' l='492' u='c'/>
<use f='src/src/sys/dev/pci/piixide.c' l='531' u='c'/>
<use f='src/src/sys/dev/pci/piixide.c' l='556' u='c'/>
<use f='src/src/sys/dev/pci/piixide.c' l='597' u='c'/>
<use f='src/src/sys/dev/pci/piixide.c' l='691' u='c'/>
<use f='src/src/sys/dev/pci/piixide.c' l='705' u='c'/>
<use f='src/src/sys/dev/pci/piixide.c' l='827' u='c'/>
<doc f='src/src/sys/dev/pci/pciide_piix_reg.h' l='45'>/*
 * IDE timing register
 * 0x40/0x41 is for primary, 0x42/0x43 for secondary channel
 */</doc>
