/* * Explanation of RECEIVE FIFO THRESHOLD: * * Controls the level at which the PCI burst state machine begins to * empty the receive FIFO. Default is "1/2 full" (0,1). * * 0,0 1/4 full 32 bytes * 0,1 1/2 full 64 bytes * 1,0 3/4 full 96 bytes * 1,1 full 128 bytes */