<dec f='src/src/sys/dev/pci/cs4280reg.h' l='50'/>
<use f='src/src/sys/dev/pci/cs4280.c' l='1416' u='c'/>
<use f='src/src/sys/dev/pci/cs4280.c' l='1447' u='c'/>
<use f='src/src/sys/dev/pci/cs4280.c' l='1451' u='c'/>
<use f='src/src/sys/dev/pci/cs4280.c' l='1452' u='c'/>
<use f='src/src/sys/dev/pci/cs4280.c' l='1592' u='c'/>
<use f='src/src/sys/dev/pci/cs4280.c' l='1595' u='c'/>
<use f='src/src/sys/dev/pci/cs4280.c' l='1612' u='c'/>
<doc f='src/src/sys/dev/pci/cs4280reg.h' l='49'>/* Clock Control Registers */</doc>
