<dec f='src/src/sys/dev/pci/pciide_cmd_reg.h' l='61'/>
<use f='src/src/sys/dev/pci/cmdide.c' l='436' u='c'/>
<doc f='src/src/sys/dev/pci/pciide_cmd_reg.h' l='57'>/*
 * data read/write timing registers . 0640 uses the same for drive 0 and 1
 * on the secondary channel
 */</doc>
