<dec f='src/src/sys/dev/ic/athnreg.h' l='50'/>
<use f='src/src/sys/dev/ic/arn5008.c' l='1195' u='c'/>
<use f='src/src/sys/dev/ic/arn9003.c' l='1354' u='c'/>
<use f='src/src/sys/dev/ic/athn.c' l='2284' u='c'/>
<dec f='src/src/sys/external/isc/atheros_hal/dist/ar5210/ar5210reg.h' l='39'/>
<use f='src/src/sys/external/isc/atheros_hal/dist/ar5210/ar5210_interrupts.c' l='49' u='c'/>
<use f='src/src/sys/external/isc/atheros_hal/dist/ar5210/ar5210_reset.c' l='164' u='c'/>
<dec f='src/src/sys/external/isc/atheros_hal/dist/ar5211/ar5211reg.h' l='49'/>
<use f='src/src/sys/external/isc/atheros_hal/dist/ar5211/ar5211_reset.c' l='405' u='c'/>
<dec f='src/src/sys/external/isc/atheros_hal/dist/ar5212/ar5212reg.h' l='46'/>
<doc f='src/src/sys/external/isc/atheros_hal/dist/ar5212/ar5212reg.h' l='45'>/* 0x5c is for QCU/DCU clock gating control on 5311 */</doc>
<use f='src/src/sys/external/isc/atheros_hal/dist/ar5212/ar5212_interrupts.c' l='61' u='c'/>
<use f='src/src/sys/external/isc/atheros_hal/dist/ar5212/ar5212_reset.c' l='440' u='c'/>
<use f='src/src/sys/external/isc/atheros_hal/dist/ar5416/ar5416_interrupts.c' l='73' u='c'/>
<use f='src/src/sys/external/isc/atheros_hal/dist/ar5416/ar5416_reset.c' l='301' u='c'/>
