<dec f='src/src/sys/dev/pci/pciide_i31244_reg.h' l='53'/>
<use f='src/src/sys/dev/pci/artsata.c' l='373' u='c'/>
<use f='src/src/sys/dev/pci/artsata.c' l='374' u='c'/>
<doc f='src/src/sys/dev/pci/pciide_i31244_reg.h' l='50'>/*
 * Extended Control and Status Register 0
 */</doc>
